Download A Designer s Guide to Built-in Self-Test by Charles E. Stroud PDF

By Charles E. Stroud

A contemporary technological enhance is the artwork of designing circuits to check themselves, often called a integrated Self-Test (BIST). This thought was once first proposed round 1980 and has grown to develop into one of many most crucial trying out suggestions on the present time, in addition to for the long run. This ebook is written from a designer's point of view and describes the main BIST ways which have been proposed and carried out due to the fact that 1980, in addition to their benefits and barriers. The BIST methods contain the integrated common sense Block Observer, pseudo-exhaustive BIST ideas, round BIST, scan-based BIST, BIST for normal buildings, BIST for FPGAs and CPLDs, mixed-signal BIST, and the combination of BIST with concurrent fault detection innovations for online checking out. specific consciousness is paid to system-level use of BIST with a view to maximize some great benefits of BIST via decreased trying out time and value in addition to excessive diagnostic answer. the writer spent 15 years as a clothier at Bell Labs the place he designed over 20 creation VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of assorted kinds for normal constructions and basic sequential good judgment, together with the first BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal platforms at Bell Labs. He has spent the previous 10 years in academia the place his examine and improvement maintains to target BIST, together with the first BIST for FPGAs and CPLDs besides persisted paintings within the sector of BIST for normal sequential good judgment and mixed-signal platforms. He holds 10 US patents (with five extra pending) for numerous kinds of BIST ways. as a result, the writer brings a different mixture of data and event to this functional advisor for designers, try out engineers, product engineers, method diagnosticians, and bosses.

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3 for an AND gate, OR gate, and inverter for all possible input patterns. Note that for each possible fault site (each input and the output of the gate) there are two possible faults that can occur, stuck-at-0 and stuck-at-1. The behavior of the gate with these faults is given in the table associated with each gate; note that this faulty behavior table assumes that only one fault is present in the gate. The output responses of the faulty gate that differ from those of the fault-free gate are highlighted in the tables by a gray background.

This facilitates toggling the input and observing the output toggle via the path sensitized through the combinational logic circuit. The delay through the path can be measured to determine if faults exist in the path which cause excessive delay. This forms the basic idea behind testing approaches for detecting delay faults [252]. 3 Undetectable Faults If no test vector or sequence of test vectors exists that can detect a given fault, then that fault is undetectable [170]. This is an interesting situation since the implication is Chapter 2.

3 Bridging Fault Models Another set of important defects includes opens in wire segments and shorts between wire segments [83]. These faults are common defects that result from over-etching or under-etching during the VLSI or PCB fabrication process. Since an open in a wire prevents the propagation of a signal past the open, inputs to gates and transistors on the other side of the open will remain constant, creating behavior equivalent to the gate-level and transistor-level fault models. As a result, opens can be detected by test vectors for either gate-level or transistor-level fault models.

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